makefile - How to write a recipe common to both .c and cpp files -
I compiled using both .c
and .cpp
files I want to do the same compiler command like
cc = G ++ ... OBJS = Mora. All: $ (oBJS) libMO.so% .o:% .c $ (CC) $ (included) $ (CCFALGS) -k $ (& lt;) -o $ (@) MBMO: $ (OBJS) $ (CC ) $ (LDFALGS) $ (^) -O Dollar (@)
The question now is that the rule / recipe for .cpp
files How is it involved? Can we do it in the same rule using the Regex for the prefix?
Is it OK to type another rule / recipe for .cpp
?
% O:% .c $ (cc) $ (included) $ (ccfalgs) - c $ (& lt;) -o $ (@)% .o:%. CPP $ (CC) $ (included) $ (CCFALGS) -C $ (& lt;) -o $ (@)
What is the above 1st recipe Another rule for Yes it is necessary that you can write a rule for each extension requirement, make the process if you redefine the same pattern. Will give the error for the 1st referral code Make That said, a small review: Special codes like C and C + code> $ (CPPFALGS) variable (for preprocessor flag, go to your C Using C ++ in GNU has already made the built-in rule for C and C ++ source files, it is correct to use the above variable, these are normal There is no need to specify the rules at all. .cpp
files for error because it can not get coding . C file? .ppp
.cpp
Is it okay to write / prescribe?
.pppp
as it file related .c
. Cpp
will process files independently from the .c
files, and vice versa (unless you explicitly tell them, for example, if any . C < / Code> file depends on a
.cpp
file.)
$ (& lt;)
or $ (@)
do not require brackets You can directly $ <
and $ @
. $ (built-in)
variable content needed). $ (CC)
and $ (CFLAGS)
uses the built-in variable: cc = $ (csea) ...% .o:% .c $ (cc) $ (cpflegs) $ (cflas) -c $ & lt;
$ (cfa)
and $ (CXXFLAGS)
built-in:
% O:% .cpp $ (CSFA) $ (CPP FALGS) $ (CFFAAGS) -C $ < -O $ @
Comments
Post a Comment